The present invention relates to semiconductor device fabrication and integrated circuits and, more specifically, to methods of forming a field-effect transistor and structures for a field effect-transistor.
Complementary-metal-oxide-semiconductor (CMOS) processes may be used to build a combination of p-type and n-type field-effect transistors that are used to construct, for example, logic cells. Field-effect transistors generally include a body defining a channel region, a source, a drain, and a gate electrode. When a control voltage exceeding a characteristic threshold voltage is applied to the gate electrode, carrier flow occurs in the channel region between the source and drain to produce a device output current.
The gate electrode may be covered by a self-aligned contact cap that protects the gate electrode during the formation of source/drain contacts. Sidewall spacers are arranged adjacent to the sidewalls of the gate electrode. The sidewall spacers may be composed of a dielectric material having a low dielectric constant. In that regard, the sidewall spacers may incorporate airgaps to form airgap spacers. In conventional process flows, the airgap spacers are formed after forming the source/drain contacts and after removing the self-aligned contact caps from their positions over the gate electrodes. Specifically, the self-aligned contact caps and sacrificial sidewall spacers are removed to generate opened spaces, and the opened spaces are refilled with portions of a dielectric layer that is non-conformally deposited. The deposited dielectric layer pinches off in the narrow portions of the spaces formerly occupied by the sidewall spacers and thereby forms the airgap spacers. The deposited dielectric layer also re-forms the self-aligned contact caps over the gate electrodes. The locations of the airgap spacers are based on the profiles of the gate electrodes and source/drain contacts, which may introduce significant variations in the locations of the airgaps and elevate the risk that the airgaps may be opened and filled with metal during downstream processing steps.
Improved structures for a field-effect transistor and methods of forming a structure for a field-effect transistor are needed.